RISC-V Core + Verification Environment
A pipelined RV32I core on a Basys 3 FPGA, checked against a reference simulator with constrained-random instruction sequences.
Why the verification half exists
Pipeline bugs often depend on the instructions next to each other. A load-use hazard or a forwarded result can fail in a sequence that a small directed test never exercises. I built the test environment alongside the core to compare each retired instruction with a Python instruction-set simulator.
The rig
- The testbench compares registers, the program counter, and memory with the reference simulator after each retired instruction.
- The generator produces legal arithmetic, memory, and branch sequences with bounded addresses and targets.
- Coverage records which opcodes, hazards, and branch outcomes the tests exercise.
- Assertions check invariants such as
x0reading zero and PC alignment.
The environment separates stimulus, checking, and coverage without depending on UVM. Passing these tests provides evidence about the exercised cases; it is not a proof that the core has no bugs.
Regression tests
Each bug gets a regression test and a record of its symptom, cause, and fix. The shorter failing sequence makes it easier to see which pipeline assumption was wrong and to check that later changes preserve the fix.